1. Field of the Invention
The present invention relates to a semiconductor device equipped with a circuit for regulating a voltage level of an internal power source by using a plurality of fuses after a fabrication of a semiconductor chip.
More specifically, in a semiconductor device capable of trimming a voltage level of an internal power source supplied to sources or drains of MOS (Metal-Oxide Semiconductor) transistors by a fuse circuit having a plurality of fuses, so as to reduce a fluctuation of this voltage level to minimum (that is, semiconductor device capable of compensating for a fluctuation component in the above voltage level that is brought about owing to the level fluctuation of the above voltage level), the present invention relates to a circuit technology which can attain a stable circuit operation, without bringing about an abnormal operation inside the semiconductor chip even when the problems associated with a glow-back or an incomplete cut-off state (i.e., insufficient cut-off state) of each of some fuses, occur.
2. Description of the Related Art
In a semiconductor device having a semiconductor chip, in general, the requirement for lowering a voltage level of a power source supplied to MOS transistors, etc., as much as possible has become stronger, in order to reduce power consumption due to the current flowing through a plurality of MOS transistors fabricated inside the semiconductor chip and to improve the endurance against the voltage applied to each of the oxide films formed in these MOS transistors.
As the voltage level of the power source supplied to the MOS transistors, etc., inside the chip is lowered so as to satisfy the requirement described above, influences due to the fluctuation of the voltage level of an external power source become greater. Therefore, it is customary to lower an external power source (VCC) to a constant voltage level inside the chip and to use this step-down voltage as the voltage level of an internal power source (VII), in order to keep flat (i.e., keep constant) the voltage level of the internal power source, by using an internal power source which is not affected by the fluctuation of the voltage level of the external power source.
FIG. 1 is a graph showing operations of the external power source (VCC) and the internal power source (VII). Here, an explanation will be given for the case in which the operating voltage Vcc of the external power source (VCC) is set to 3.3 V as a typical example.
According to specifications placed in catalogues of products of semiconductor devices in which the operating voltage Vcc=3.3 V is stipulated as the external power source (VCC), a recommended operating condition (i.e. recommended operating range) of each of these products of semiconductor devices is Vcc=3.0 V to 3.6 V. However, an internal power source (VII) which is controlled so as to become flat (i.e., remain constant) at the operating voltage Vo of 2.4 V (here, the value of 2.4 V is a design target value or "default value", and an operating voltage range of the internal power source (VII) ranging from 2.0 V to 2.8 V, for example, is permitted) is used in practice so as to flatten the voltage level as described above. It should be noted, however, that there is the case in which an arbitrary voltage level of the internal power source within the operating voltage range described above cannot be obtained after fabrication of the chip, owing to the fluctuation of process conditions during the fabrication of the chip, or the like. In such a case, the voltage level of the internal power source must be regulated by a fuse circuit having a plurality of fuses as will be described later.
FIGS. 2 and 3 are the first part and the second part of a circuit block diagram showing the mode of the regulation of the internal power source voltage level in a semiconductor device according to the prior art, respectively. In this case, the construction of the semiconductor device is shown in a simplified form.
In the semiconductor device according to the prior art shown in FIG. 2, there are disposed a fuse circuit 120 for trimming an internal power source which is equipped with a plurality of fuses F each being capable of taking a cut-off state as a circuit having the function of regulating a voltage level of an internal power source; and a decoding circuit 130 for fuse information of an internal power source, which decodes fuse information (i.e., output signals rff0x, rff1x and rff2x of the fuse circuit for trimming the internal power source) relating to the cut-off state of the fuses F obtained from the fuse circuit 120, and which converts the above fuse information to bit information associated with the voltage level of the internal power source (decode signals f1t0x to f1t4x and f1t0z to f1t4z).
In the semiconductor device according to the prior art shown in FIG. 3, further, there are disposed an internal power source control circuit 50 which outputs a gate control voltage Vrfv for generating a voltage level of a design target value in accordance with the bit information outputted from the decoding circuit 130 for fuse information of the internal power source; and an internal power source generating circuit 60 which lowers the external power source VCC in accordance with the gate control voltage Vrfv outputted from the internal power source control circuit 50 and which converts the external power source to the internal power source VII (i.e., a step-down internal power source).
In the circuit construction described above, the final voltage level of the step-down internal power source VII is decided by the fuse circuit 120 for trimming the internal power source, the decoding circuit 130 for fuse information of the internal power source, the internal power source control circuit 50 and the internal power source generating circuit 60.
In the example of the circuit for regulating the voltage level of the internal power source described above, a transistor 61 for stepping down the external power source inside the internal power source generating circuit 60 includes an N channel type transistor, but the transistor 61 is not particularly limited to this N channel type transistor. The method of stepping down and controlling the power source converts the external power source VCC to the internal power source VII by regulating the potential of the gate of the transistor 61 for stepping down the external power source. In other words, one of the junctions (nodes) of a plurality of level regulating resistors 57 is selected by operating any one of a plurality of transfer gates 0a to 4a inside the transfer gate circuit unit 56 in the internal power source control circuit 50 shown in FIG. 3, and it is possible to carry out the conversion operation from the external power source VCC to the internal power source VII by regulating the voltage level of the output node (gate control voltage (Vrfv)). Each of a plurality of transfer gates described above includes a CMOS transistor having a P channel type transistor and an N channel type transistor. The arrow attached to the P channel type transistor represents back-bias applied to the gate of the P channel type transistor. Incidentally, the circuit construction of the internal power source control circuit 50 shown in FIG. 3 will be described in further detail in the paragraph "DESCRIPTION OF THE PREFERRED EMBODIMENTS".
The voltage level of the gate control voltage Vrfv is originally determined by the internal power source control circuit 50 shown in FIG. 3. However, if semiconductor devices are fabricated and manufactured into products under an undesirable condition such as a fluctuation of process conditions during the fabrication of the chip, the internal power source VII having a design target voltage level, that is, the gate control voltage Vrfv having a necessary voltage level, cannot be outputted in most cases, as shown in FIG. 1.
The prior art example shown in FIGS. 2 and 3 is equipped with the fuse circuit 120 for trimming the internal power source and the decoding circuit 130 for fuse information of the internal power source 130 in order to accurately regulate the voltage level of the internal power source VII after the process for fabricating the chip is completed.
The prior art example described above is of the type which can regulate the voltage level of the gate control voltage Vrfv to the design target voltage level by regulating the resistance value of the level regulating resistors 57 inside the internal power source control circuit 50. Fuse information relating to the cut-off state of each of a plurality of fuses (for examples, three pairs of fuses) inside the fuse circuit 120 for trimming the internal power source shown in FIG. 2, are inputted in the form of the output signals rff0x to rff2x of the three fuse circuits for trimming the internal power source to three inverters 300 to 320 for decoding the fuse information inside the decoding circuit 130 for fuse information of the internal power source, through level converting circuit units 200 to 220, respectively. NAND gates 330 to 334 for generating the fuse information patterns, inside this decoding circuit 130 for fuse information of the internal power source, decode the fuse information on the basis of the input signals (non-inversion signals) and the output signals (inversion signals) of the inverters 300 to 320 for decoding the fuse information. Further binary bit information associated with the voltage levels of the internal power source (decode signals f1t0x to f1t4x and f1t0z to f1t4z) is outputted through the inverters 340 to 344 for generating the fuse information patterns. In other words, any one of a plurality of transfer gates 0a to 4a of the internal power source control circuit 50 shown in FIG. 3 is operated on the basis of the decoding result of the fuse information described above so as to regulate the resistance value of the level regulating resistor 57 and to thus generate the gate control voltage Vrfv of an arbitrary level. By the way, the fuse circuit 120 for trimming the internal power source and the decoding circuit 130 for the fuse information of the internal power source are hereby constituted by the inverters and the NAND gates, but they should not be limited to the inverters and the NAND gates.
In the prior art example described above, the level regulating resistors 57 inside the internal power source control circuit 50 are selected in accordance with five bit information patterns shown at the right part of FIG. 3 so as to trim the voltage level of the internal power source. The design target value (i.e. default value) of the voltage level of the internal power source is the center value of the operating voltage range, and the case in which the output levels of the decode signals f1t2x and f1t2z are "L" (Low) and "HI" (High), respectively, and the transfer gate 2a is selected, corresponds to the case in which the voltage level of the internal power source is regulated so as to attain the design target value described above.
The power source voltage levels that can be set to levels higher and lower than the design target value by two points, respectively, define the voltage range which can be trimmed by the selection of the level regulating resistors 57. When the operating voltage Vo of the internal power source VII becomes higher or lower than the operating voltage range due to a fluctuation of process conditions during the fabrication of the chip or the like, as shown in FIG. 1, the operating voltage can be regulated in the range of the voltage level covered by the above two points in both the upward and downward directions of the operating voltage level.
In order to illustrate the transfer gate which is selected by the internal power source control circuit 50, when the upper fuse or the lower fuse in each pair of fuses inside the fuse circuit 120 for trimming the internal power source are selectively cut off, FIG. 4 shows the relationship between a fuse selection and an output level in the prior art construction.
To select the five bit information described above, it is necessary to prepare a plurality of fuses corresponding to the number of fuses that is necessary for representing at least bit information of at least three bits (2.sup.3 =8). The fuse circuit 120 for trimming the internal power source described above can represent 3-bit (three-bit) information by using three pairs of fuses. When either one of the upper fuse and the lower fuse in each pair of fuses connected to the power source for the drain (here, the external power source VCC) and the power source for the source (here, the power source with the ground level VSS) is cut off, the decoding circuit 130 for fuse information of the internal power source is allowed to distinguish between "0" and "1", respectively.
In the fuse circuit 120 for trimming the internal power source, when the upper fuse is cut off, the node #k (here, k=0 to 2) is set to the voltage level of the power source for the source (approximately 0V) and the potential of this node #k is converted to a high logic level by the level converting circuit units 200 to 220. Therefore, the level of the output signal rff#k of the fuse circuit for trimming the internal power source changes to the level "H" (here, #=0 to 2; rff#x="H"). When the lower fuse is cut off, the node #k (here, k=0 to 2) is set to the voltage level of the power source for the drain (approximately Vcc), and the potential of this node #k is converted to a low logic level by the level converting circuit units 200 to 220. Therefore, the level of the output signal rff#x of the fuse circuit for trimming the internal power source changes to the level "L" (rff#x="L"). Furthermore, when the output signals rff0x to rff2x of the fuse circuit for trimming the internal power source sent from all the nodes #0 to #2 are decoded by the decoding circuit 130 for fuse information of the internal power source, the resistance values of the level regulating resistors 57 used in the internal power source control circuit 50, are decided.
Symbols 0x, 1x and 2x in FIG. 4 (or FIG. 3) represent #x of the output signals rff#x of the fuse circuit for trimming the internal power source, and also represent fuse information relating to the cut-off state of each of the fuses at all the nodes #0 to #2 on the fuse-cut side. In other words, these 0x, 1x and 2x represent the level of three inputs of a plurality of NAND gates for generating fuse information patterns for operating any one of the transfer gates 0a to 4a of the internal power source control circuit 50 shown in FIG. 3.
When the first transfer gate 0a disposed in the uppermost portion of these transfer gates 0a to 4a inside the internal power source control circuit 50 (FIG. 3) is desired to be selectively turned ON (i.e., to the operating state), for example, as shown in FIG. 4, the fuse for 0x in the NAND gate 330 for generating the fuse information, which is connected to this transfer gate 0a, is cut off so as to select the level "L", the fuse for 1x is also cut off so as to select the level "L", and the fuse for 2x, too, is cut off so as to select the level "L".
On the other hand, when the fifth transfer gate 4a of the lowermost portion of the transfer gates 0a to 4a inside the internal power source control circuit 50 is desired to be selectively turned ON, the fuse for 0x in the NAND gate 334 for generating the fuse information pattern, which is connected to this transfer gate 4a, is cut off so as to select the level "L", the fuse for 1x is also cut off so as to select the level "L" and only the fuse for 2x is cut off so as to select the level "H".
However, in the circuit having the function of regulating the voltage level of the internal power source according to the prior art described above, the fuse circuit such as the fuse circuit for trimming the internal power source is used in order to regulate this voltage level after the process for fabricating the chip is completed. Accordingly, this circuit involves the following problem.
A phenomenon referred to as a "glow-back" sometimes occurs in this circuit. The term "glow-back" hereby represents the phenomenon in which the fuse which should have been cut off by using a laser, etc., is not sufficiently cut off and remains in an incomplete cut-off state, or the phenomenon in which the fuse returns to the state before the cut-off state due to a stress caused by heat or voltage. Speaking electrically, this phenomenon means the case in which a resistance value of the portion which should attain a high resistance value after a cut-off of a given fuse changes to a low resistance value due to the glow-back (when the cut-off of the fuse is carried out insufficiently, the fuse remains in a low resistance value from the beginning).
When the voltage level of the internal power source has the design target value (i.e. default value) in the case of the fuse circuit for trimming the internal power source shown in FIG. 2, the fuse for 0x is cut off so as to select the level "L", the fuse for 1x is cut off so as to select the level "H" and the fuse for 2x is selected so as to select the level "L". In other words, the fuses at the nodes #0 to #2 inside the fuse circuit for trimming the internal power source may be cut off so as to select the level "L", "H" and "L", respectively. When such a process for cutting off fuses is carried out, the circuit operation is executed so that the third transfer gate 2a disposed in the central portion of the transfer gates 0a to 4a, for regulating the resistance value of the level regulating resistors 57 inside the internal power source control circuit 50, is selected.
On the other hand, the phenomenon brought about when a glow-back has occurred in the fuse circuit for trimming the internal power source will be considered.
The construction of this fuse circuit for trimming the internal power source is set so that the output signal rff#x of the fuse circuit for trimming the internal power source outputs the level "L" before the fuses are cut off. Therefore, the resistance value of the level regulating resistor 57 inside the internal power source control circuit 50, which is selected immediately after the completion of the process for fabricating the chip, is decided by the node connected to the first transfer gate 0a disposed in the uppermost portion of the transfer gates 0a to 4a.
Further, the fuses are cut off so as to attain an arbitrary value after the voltage level of the internal power source VII is measured. However, when all the fuses that are cut off undergo a glow-back, the node connected to the first transfer gate 0a is selected. In this case, a potential corresponding to a certain voltage level is supplied to this node through the transfer gate 0a and no critical problem occurs.
However, when only a certain fuse or only a portion of this fuse is in an incomplete cut-off state, and the pattern of bit information constituted by this incomplete cut-off state is a pattern other than the patterns of the five bit information described above, that is, when a given unnecessary pattern which is shown at the lower part of FIG. 4 and is not used at present is selected, all the transfer gates change to the OFF state (i.e., the non-operating state) and the overall circuitry inclusive of the fuse circuit 120 for trimming the internal power source, the decoding circuit 130 for fuse information of the internal power source and the internal power source control circuit 50 becomes unstable. In consequence, the problem occurs in that the semiconductor chip in which this circuit is formed carries out an abnormal operation.